Low temperature hybrid wafer bonding for 3D integration

Author

Damian, A.A. ; Poelma, R.H. ; van Zeijl, H.W. ; Zhang, G.Q.

Author_Institution

Lab. of ECTM, Delft Univ. of Technol., Delft, Netherlands

fYear

2013

fDate

14-17 April 2013

Firstpage

1

Lastpage

5

Abstract

Techniques for the bonding of wafers and dies at low temperature are investigated. Controlled wet etching using acids is used to bond SiO₂-SiO₂ and Al-Al chips at room temperature. The bond strength is evaluated using die-shear tests. Infrared imaging and SEM analysis are used to inspect the bonding interface. The results are compared with data from fusion bonding experiments. Relatively high bond bond strengths for SiO₂ and Al-terminated chips are achieved using bonding at room temperature.

Keywords

aluminium; low-temperature techniques; silicon compounds; three-dimensional integrated circuits; wafer bonding; 3D integration; SEM analysis; bonding interface; controlled wet etching; die-shear tests; fusion bonding; infrared imaging; low temperature hybrid wafer bonding; room temperature; temperature 293 K to 298 K; Abstracts; Annealing; Hafnium; Micromechanical devices; Silicon; Standards;

fLanguage

English

Publisher

ieee

Conference_Titel

Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2013 14th International Conference on

Conference_Location

Wroclaw

Print_ISBN

978-1-4673-6138-5

Type

conf

DOI

10.1109/EuroSimE.2013.6529968

Filename

6529968