FPGA implementation of fast adder

This paper proposes high data rate implementation of an adder on Field Programmable Gate Arrays (FPGA). Digital Signal processing applications are characterized by the data rate or the throughput of the system. Optimal hardware implementation on FPGA is differentiated from other hardware design platforms due to its fixed fabric and routing structure. Implementation of different adder architectures has been compared based on their clock speeds and the resource utilization. Experimental results have shown that traditional hardware optimizations perform adversely after implementation on FPGAs, where the Ripple Carry Adder has shown clock speed gain of a minimum of 18.24% using 50% lesser resources for two operand multipliers. In case of multi-operand additions the Carry Save Addition compressor trees have outperformed other techniques by 7.89% increase in clock speed at the expense of 28.17% increase in hardware resources.