Simulation and implementation of LDPC code in FPGA

The paper deals with implementation of Low-Density Parity-Check (LDPC) codes [1] in FPGA-based bridge for Free-Space Optical link. The coder was designed with a regular parity matrix for code rate 1/2. The matrix of dimension 8×16 for the experimental implementation was found using a random search in MATLAB. The main advantage of this matrix is the decoder can correct all single-bit errors. The simulation for all possible values shows that Bit Error Ratio (BER) is zero. This result was not obtained with other matrices. An experimental communication channel was realized with encoder and decoder implemented in FPGA Virtex 5 development board ML505. DIP switches are sources for information bits and these values are shown on LCD display. The bit-flipping method is used in decoder and result code word is shown in the second line on the LCD display.