Title :
Reed-solomon decoder hardware implementation for DVB-S receiver
Author :
Dilek, Seyyid M. ; Ors, B. ; Kartal, M.
Author_Institution :
Elektron. ve Haberlesme Muhendisligi Bolumu, Istanbul Teknik Univ., Istanbul, Turkey
Abstract :
In this paper, a shortened Reed-Solomon decoder (n=204, k=188) is simulated using MATLAB and Maple programs within Digital Video Broadcasting - Satellite standards. Then, it is modelled and its hardware is implemented regarding to speedy, flexible, and straightforward production on FPGA using VHDL. Due to speed, flexibleness, and easy fabrication, the cellular-array multiplication method is used for the commonly used arithmetic operation, finite field multiplication. Reformulated inverse-free Berlekamp-Messey Algorithm, capable of high speed and low complexity, is implemented succesfully for key equation solver unit.
Keywords :
Reed-Solomon codes; cellular arrays; digital video broadcasting; direct broadcasting by satellite; field programmable gate arrays; hardware description languages; radio receivers; DVB-S receiver; FPGA; Maple programs; Matlab; Reed-solomon decoder hardware implementation; Reformulated inverse-free Berlekamp-Messey Algorithm; VHDL; arithmetic operation; cellular-array multiplication method; digital video broadcasting-satellite standards; finite field multiplication; key equation solver unit; Blogs; Computer architecture; Decoding; Digital video broadcasting; Field programmable gate arrays; Reed-Solomon codes; Very large scale integration; DVB-S; FPGA; Reed-Solomon; RiBM; VHDL;
Conference_Titel :
Signal Processing and Communications Applications Conference (SIU), 2013 21st
Conference_Location :
Haspolat
Print_ISBN :
978-1-4673-5562-9
Electronic_ISBN :
978-1-4673-5561-2
DOI :
10.1109/SIU.2013.6531372
