The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server

Author

Kan, Ryuji ; Tanaka, T. ; Sugizaki, G. ; Ishizaka, K. ; Nishiyama, R. ; Sakabayashi, S. ; Koyanagi, Yoshio ; Iwatsuki, R. ; Hayasaka, K. ; Uemura, Toshifumi ; Ito, G. ; Ozeki, Yasuyuki ; Adachi, H. ; Furuya, Keiichi ; Motokurumada, T.

Author_Institution

Fujitsu, Kawasaki, Japan

Volume

49

Issue

1

fYear

2014

fDate

Jan. 2014

Firstpage

32

Lastpage

40

Abstract

A 10th generation SPARC64 processor, fabricated in enhanced 28 nm CMOS, runs at 3.0 GHz and contains 16 cores with 24 MB shared L2 cache and system/DDR3/PCIe interfaces in 588 mm² die area. Using H-tree clock distribution network with shield wires, the average clock skew is minimized to 20 ps. Two-step read structure of GPR enables out-of-order execution across register windows. A large SMP system of up to 64 CPUs with ccNUMA uses a newly developed 14.5 GB/s SerDes. Column separation, alternate placement of master and slave latches and well slits are used to mitigate soft errors especially for multi-bit upsets. SER reduction is observed by neutron irradiation experiments.

Keywords

CMOS integrated circuits; Unix; cache storage; clocks; microprocessor chips; radiation hardening (electronics); CMOS; CPU; GPR; H-tree clock distribution network; L2 cache; SER reduction; SMP system; average clock skew; ccNUMA; column separation; die area; frequency 3 GHz; master latches; multibit upsets; neutron irradiation experiments; register windows; shield wires; size 28 nm; slave latches; soft errors; system/DDR3/PCIe interfaces; two-step read structure; Clocks; Ground penetrating radar; Latches; Pipelines; Registers; Timing; Wires; Clock distribution; SPARC; computer architecture; high-speed SerDes; microprocessor; register file; reliability; soft error; test;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2013.2284650

Filename

6642130