Title :
Analysis on static noise margin improvement in 40nm 6T-SRAM with post-process local electron injected asymmetric pass gate transistor
Author :
Miyaji, K. ; Kobayashi, Daiki ; Takeuchi, Ken ; Miyano, S.
Author_Institution :
Dept. of Electr., Electron., & Commun. Eng., Chuo Univ., Tokyo, Japan
Abstract :
Improvement of the static noise margin (SNM) in 40nm 6T-SRAM with local electron injected asymmetric pass gate (PG) transistor is analyzed. Lower word-line voltage during injection shows higher PG VTH shift and SNM improvement. SNM variation decreases by 13.6% after injection using pseudo disturb. Pull up transistor |VTH| decrease degrades write margin. Under voltage and thermal retention stress, average SNM improvement of the worst 10 cells out of 1k cells decreases by 7.0% at 3.4×105s.
Keywords :
SRAM chips; transistor circuits; 6T-SRAM; SNM improvement; local electron injected asymmetric PG transistor; local electron injected asymmetric pass gate transistor; post-process local electron injected asymmetric pass gate transistor; pseudo disturb; size 40 nm; static noise margin improvement; thermal retention stress; word-line voltage; Logic gates; Noise; Random access memory; Stress; Thermal stability; Transistors; Voltage measurement; Hot electron injection; SRAM; Self-repair; Static noise margin; Variability;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2013 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4799-0112-8
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2013.6531982
