Advances in industrial practices for optimal performance/reliability/power trade-off in commercial high-performance microprocessors for wireless applications

Author

Huard, Vincent ; Cacho, F. ; Claramond, L. ; Alves, P. ; Dalkowski, W. ; Jacquet, D. ; Lecomte, S. ; Tan, Min ; Delemer, B. ; Kamoun, A. ; Fraisse, V.

Author_Institution

STMicroelectron., Crolles, France

fYear

2013

fDate

14-18 April 2013

Abstract

This paper deals with the challenge of optimizing the performance/reliability/power trade-off in commercial high-performance microprocessors for wireless applications in advanced CMOS nodes. Both the increased impact of electrical reliability degradation and an increased thermal runaway risk require a dedicated approach combining product engineering and high-level modeling approach to achieve optimal reliability guardband determination even in the case of numerous, discrete V-F operating modes and their related mission profiles.

Keywords

CMOS integrated circuits; industrial engineering; microprocessor chips; radio networks; reliability; CMOS nodes; commercial high-performance microprocessors; discrete V-F operating modes; electrical reliability degradation; high-level modeling approach; industrial practices; optimal performance-reliability-power trade-off; optimal reliability guardband determination; product engineering; thermal runaway risk; wireless applications; Aging; Microprocessors; Phase locked loops; Program processors; Reliability engineering; Voltage measurement; AVS; DVFS; aged models; failure rate; gate-level models; guardband; microprocessor; product qualification; reliability; wireless application;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium (IRPS), 2013 IEEE International

Conference_Location

Anaheim, CA

ISSN

1541-7026

Print_ISBN

978-1-4799-0112-8

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2013.6531998

Filename

6531998