Sub-threshold current based acceleration and modeling of OFF-state TDDB in drain extended NMOS and PMOS transistors

It is not always practical to observe OFF-state drain-to-gate dielectric breakdown in power transistors due to the upper limit set to stress voltage by junction breakdown. In this paper we demonstrate that OFF-state breakdown in drain extended power transistors can be accelerated by increasing the channel current (I_S) by biasing the transistor in sub-threshold. We also show that the charge pumping scaling factors along with observed breakdown times can be used to build an I_S and V_DG dependent model to extrapolate failure times at operating bias conditions.