Title :
Effect of TSV presence on FEOL yield and reliability
Author :
Kauerauf, T. ; Branka, A. ; Croes, Kristof ; Redolfi, A. ; Civale, Y. ; Torregiani, C. ; Groeseneken, Guido ; Beyne, Eric
Author_Institution :
imec, Leuven, Belgium
Abstract :
In this work we evaluate the impact of TSV processing and proximity on transistor performance and reliability by monitoring key device parameters after thermal cycling and thermal storage. No transistor degradation related to potential barrier failure, liner breakdown or Cu diffusion was observed and it is concluded that when respecting the keep out zone, the FEOL yield and reliability is not affected by TSV processing.
Keywords :
CMOS integrated circuits; MOSFET; copper alloys; failure analysis; high-k dielectric thin films; integrated circuit reliability; semiconductor device breakdown; three-dimensional integrated circuits; Cu; FEOL yield; HKMG CMOS; TSV effect; TSV processing; liner breakdown; potential barrier failure; reliability; thermal cycling; thermal storage; through silicon vias; transistor performance; Integrated circuit reliability; MOS devices; Stress; Thermal stresses; Through-silicon vias; Transistors; TSV; keep out zone; reliability; yield;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2013 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4799-0112-8
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2013.6532035
