Title :
Impact of cell distance and well-contact density on neutron-induced Multiple Cell Upsets
Author :
Furuta, J. ; Kobayashi, Kaoru ; Onodera, Hidetoshi
Author_Institution :
Grad. Sch. of Inf., Kyoto Univ., Kyoto, Japan
Abstract :
We measured neutron-induced Single Event Upsets (SEUs) and Multiple Cell Upsets (MCUs) on Flip-Flops (FFs) in a 65 nm bulk CMOS process. Measurement results show that MCU / SEU is up to 23.4% and is exponentially decreased by the distance between latches on FFs. MCU rates can drastically be reduced by inserting well-contact arrays between FFs. The number of MCUs is reduced from 110 to 1 by inserting a well-contact array under power and ground rails.
Keywords :
CMOS logic circuits; electrical contacts; flip-flops; neutron effects; FF; MCU rates; SEU; bulk CMOS process; cell distance; flip-flops; ground rails; neutron-induced multiple cell upsets; power rails; size 65 nm; well-contact arrays; well-contact density; Clocks; Inverters; Latches; Neutrons; Reliability; Resilience; Shift registers;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2013 IEEE International
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-4799-0112-8
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2013.6532053
