Investigation of single-trap-induced random telegraph noise for tunnel FET based devices, 8T SRAM cell, and sense amplifiers

This paper analyzes the impacts of Random Telegraph Noise (RTN) caused by a single acceptor-type trap on Tunnel FET (TFET) based devices, 8T SRAM cell and sense amplifiers. 3D atomistic TCAD simulations accounting for the impact of localized/negatively-charged trap are utilized to assess the dependence of RTN amplitude (ΔI_D/I_D) on trap location and device geometry. Our results indicate that significant RTN impact occurs for trap located near the tunneling junction. The device design strategies (thinner EOT, W_fin and longer L_eff) to improve TFET device characteristics are found to increase the susceptibility to RTN. Furthermore, TFET-based standard 8T SRAM cell and several commonly used sense amplifiers including Current Latch Sense Amplifier (CLSA), Voltage Latch Sense Amplifier (VLSA), and single-ended large-signal inverter sense amplifier are examined using atomistic 3D TCAD mixed-mode simulations. The presence of RTN is shown to cause extra ~16% variations in cell stability (at V_dd = 0.3V) and additional ~80mV variation in offset voltage for sense amplifiers at V_dd = 0.5V.