Author :
Pandey, Bishwajeet ; Yadav, J. ; Pattanaik, Manisha ; Rajoria, N.
Author_Institution :
Dept. of Inf. Technol., ABV-Indian Inst. of Inf. Technol. & Manage., Gwalior, India
Abstract :
In this paper, latch free clock gating techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and 55.78% of total dynamic power when device operating frequency is 100MHz, 1GHz, 10GHz, 100GHz and 1 THz. After implementation of clock gating techniques in ALU, Clock power reduces to 17.85%, 23.39%, 26.49% and 27.19% of total dynamic power, when device operating frequency is 1GHz, 10GHz, 100GHz and 1 THz. On 1 THz operating frequency, when we use clock gating, there are 72.77% reduction in clock power, 38.88% reduction in IOs power and 44% reduction in dynamic power in compare to power consumption without using clock gating techniques. Target device is 90-nm Spartan-3. There is 14.57% reduction in junction temperature on 10GHz operating frequency in compare to temperature without using clock gating techniques. Clock gating saves power but increases over all area. There is 32.35%, 37.84%, 43.31% and 44% reduction in dynamic current when we use clock gate on 1GHz, 10GHz, 100GHz and 1THz operating frequency respectively.
Keywords :
clocks; digital arithmetic; energy conservation; field programmable gate arrays; logic design; power consumption; FPGA implementation; IOs power reduction; clock gating based energy efficient alu design; clock power reduction; device operating frequency; dynamic power consumption; frequency 1 GHz; frequency 1 THz; frequency 10 GHz; frequency 100 GHz; frequency 100 MHz; junction temperature reduction; latch free clock gating technique; Clocks; Conferences; Field programmable gate arrays; Junctions; Logic gates; Power demand; Registers; Clock Gating; Clock Power; Dynamic Current; Dynamic Power; Energy Efficient; Low Power; Operating Frequency;
