The quest for a new dimension of system integration

Summary form only given. While innovation in manufacturing continues to push the envelope of CMOS device scaling toward the physical limit, at the meantime, system integration has found an alternative path to delay the limitation by using silicon-interposer based design with through-silicon-via (TSV) or true 3-D IC die stacking to cram more devices within the same chip pacakge. These solutions enable tight integration of heterogeneous processes, miniaturize the overall footprint of a sub-system, and provide shorter interconncet with higher bandwidth, thereby improving both the power and performance. In this talk, I will describe the evolutionary endeavor to the realization of 3-D IC. I will then discuss the latest Chip-on-Wafer-on-Substrate (CoWoS) technology offered by TSMC and the test vehicle implementation with wide I/O DRAM, followed by my view of the prospect of true 3-D die stacking.