Title :
The quest for a new dimension of system integration
Author :
Lee, Hsien-Hsin S.
Author_Institution :
TSMC, Georgia Tech Univ., Atlanta, GA, USA
Abstract :
Summary form only given. While innovation in manufacturing continues to push the envelope of CMOS device scaling toward the physical limit, at the meantime, system integration has found an alternative path to delay the limitation by using silicon-interposer based design with through-silicon-via (TSV) or true 3-D IC die stacking to cram more devices within the same chip pacakge. These solutions enable tight integration of heterogeneous processes, miniaturize the overall footprint of a sub-system, and provide shorter interconncet with higher bandwidth, thereby improving both the power and performance. In this talk, I will describe the evolutionary endeavor to the realization of 3-D IC. I will then discuss the latest Chip-on-Wafer-on-Substrate (CoWoS) technology offered by TSMC and the test vehicle implementation with wide I/O DRAM, followed by my view of the prospect of true 3-D die stacking.
Keywords :
DRAM chips; three-dimensional integrated circuits; 3D IC die stacking; CMOS device scaling; I/O DRAM; TSV; chip on wafer on substrate technology; chip package; manufacturing innovation; silicon interposer based design; system integration; test vehicle implementation; through silicon via; CMOS integrated circuits; CMOS technology; Educational institutions; Manufacturing; Stacking; Technological innovation;
Conference_Titel :
VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4673-4435-7
DOI :
10.1109/VLDI-DAT.2013.6533799
