A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS

Author

Kunzhi Yu ; Xuqiang Zheng ; Ke Huang ; Ma Xuan ; Ziqiang Wang ; Chun Zhang ; Zhihua Wang

Author_Institution

Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China

fYear

2013

fDate

22-24 April 2013

Firstpage

1

Lastpage

4

Abstract

This paper presents a source synchronous receiver data lane design in 65nm CMOS process. The data lane circuit consists of a pre-amplifier which can compensate over 8dB channel loss and a half-rate digital CDR based on phase-interpolator. The CDR bandwidth is programmable by using a digital FIR filter. This design uses variable offset amplifier technology to increase sensitivity of the receiver. And a common-mode level shift function is implemented in order to increase the bandwidth of the pre-amplifier. The area for one data channel without ESD and PAD is 0.05 mm^2 and power consumption is 35mw for 1.2V supply.

Keywords

CMOS digital integrated circuits; FIR filters; clock and data recovery circuits; equalisers; interpolation; preamplifiers; CDR bandwidth; CMOS process; bit rate 6.4 Gbit/s; channel loss; common-mode level shift function; data lane circuit; digital FIR filter; half-rate digital CDR; phase-interpolator; power 35 mW; preamplifier; size 65 nm; source synchronous receiver core; variable offset amplifier technology; variable offset equalizer; voltage 1.2 V; Bandwidth; CMOS integrated circuits; Clocks; Finite impulse response filters; Jitter; Receivers; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4673-4435-7

Type

conf

DOI

10.1109/VLDI-DAT.2013.6533835

Filename

6533835