A view scalable multi-view video decoder system

This paper presents a view scalable multi-view video decoder system that integrates multiple decoder cores into the proposed system to decode multi-view video and achieve parallel decoding with high view scalability. We manage the firmware for video bit-stream partition and design an arbitration mechanism to balance the work load among decoder cores with a 4KB two-level cache architecture for inter-view/inter-frame prediction data reusing. With such a flexible architecture, the proposed system can reach 1.8 times performance improvement with two decoding cores and 3.5 times with four decoding cores. Based on the proposed system, users only need to adjust the number of decoder cores and set the firmware parameters for different system applications. This feature also benefits to adopting 3D IC packaging or implementation to exploit high bandwidth DRAM access. The proposed view scalable multi-view video decoder system is able to decode multiple-view HD video in real time.