An FPGA-based test platform for analyzing data retention time distribution of DRAMs

Author

Chih-Sheng Hou ; Jin-Fu Li ; Chih-Yen Lo ; Ding-Ming Kwai ; Yung-Fa Chou ; Cheng-Wen Wu

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Jhongli, Taiwan

fYear

2013

fDate

22-24 April 2013

Firstpage

1

Lastpage

4

Abstract

Data retention time distribution of a dynamic random access memory (DRAM) has a heavy impact on its yield, power, and performance. Accurate and detailed information of data retention time distribution thus is very important for the DRAM designer and user. This paper proposes an FPGA-based test platform for analyzing the data retention time distribution of a DRAM. Based on the test platform, a test flow is also proposed to classify the DRAM cells with different data retention times with respect to different supply voltage and temperature. We have demonstrated the test platform and test flow using a Micron 2Gb DRAM.

Keywords

DRAM chips; field programmable gate arrays; logic testing; DRAM data retention time distribution analysis; FPGA-based test platform; Micron DRAM; dynamic random access memory; field programmable gate arrays; Built-in self-test; Circuit faults; Current measurement; Leakage currents; Random access memory; Temperature distribution; Temperature measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4673-4435-7

Type

conf

DOI

10.1109/VLDI-DAT.2013.6533853

Filename

6533853