Electromigration- and obstacle-avoiding routing tree construction

As the layout complexity of analog ICs increases, designers must spend more effort in dealing with the routing problem. A major issue is the constraint of the wire current density. Because the negligence of circuit designers or the channel space constraints between obstacles lead to the wire width too thin, making the wire current density is too high. This condition causes electromigration phenomenon and a permanent failure. However, widening wire widths arbitrarily to reduce the current density leads to larger wire area and routing resource. This paper proposes a routing method for analog ICs with considering obstacles and the channel space constraints. Experimental results show that the proposed method guarantees that all wire widths can conform to the DRC of channels with minimum wire area.