Wafer thinning and back side processing to enable 3D stacking

We report on the several processes defined and executed for generating ultra thin 3D devices. The devices used have been processed on 200mm wafers using 130nm CMOS technology with TSVs. We focus on processes like wafer thinning, backside passivation, back side RDL (Re-Distribution Layer), front side and backside μbumping. We finally present the electrical characterization of manufactured 3D stacks executed in case of two-dies stacking and three-dies stacking. Functional chains of different lengths based on the number of TSVs-μbumps forming the chain (10, 30, and 252 TSVs-μbumps) were measured.