Demonstration of integrating post-thinning clean and TSV exposure recess etch into a wafer backside thinning process

The development of 3D-SIC technology has been requiring more delicate backside processing with increasing complexity and process requirements. As one of the key enabling process steps, wafer backside thinning must also evolve to satisfy the emerging demands. In addition to extreme wafer thickness control, the process requirements has also been extended into contamination control and cost reduction aspects, etc. In this work, we demonstrated a novel wafer backside thinning process integrated with post thinning clean and TSVs exposure recess etch in the context of imec´s 300 mm wafer backside integration scheme. We expected that implementation of this process in the production line could dramatically simplify and eventually reduce the totally cost of wafer backside processing for 3D-SIC.