Title :
3D SiP module using TSV and novel low-volume solder-on-pad(SoP) process
Author :
Bae, Hyun-Cheol ; Bae, Ho-Eun ; Jeon, Su-Jeong ; Jung, Kwang-Hoon ; Eom, Yong-Sung ; Choi, Kwang-Seong
Author_Institution :
Packaging Research Team, Convergence Components & Materials Research Laboratory, Electronics and Telecommunications Research Institute, 138 Gajeongro, Yuseong-gu, Daejeon, 305-700, Korea
Abstract :
In this paper, a three-dimensional system in packaging (3D SiP) module in which a bottom interposer and a top interposer are interconnected vertically with the low-volume solder-on-pad (SoP) and through-silicon vias (TSVs) has been presented. A novel solder bumping material has been developed for the low-volume SoP and the thickness of SoP was measured about 10 μm. The low-volume SoP was evaluated by the cross-sectional photographs and the measurement of dc resistance using daisy-chain patterns. 3D SiP module composed of a GPU and two SRAM on the interposers were fabricated with this bumping material, a fluxless underfill and the vertical interconnection processes.
Conference_Titel :
Electronic System-Integration Technology Conference (ESTC), 2012 4th
Conference_Location :
Amsterdam, Netherlands
Print_ISBN :
978-1-4673-4645-0
DOI :
10.1109/ESTC.2012.6542209