Title :
A high-speed and low-power up/down counter in 0.18-μm CMOS technology
Author :
Tangbiao Zhang ; Qingsheng Hu
Author_Institution :
Jiangsu Provincial Key Lab. of Sensor Network Technol., Southeast Univ., Wuxi, China
Abstract :
A high speed and power efficient up/down counter is proposed in this paper. Straightforward circuit architecture is adopted for the counter, thus the area and power penalty can be saved. Additionally, several timing optimal methods including logic effort, full-custom methodology for key components and elaborate manual placement and routing are employed to minimize the delay and improve the working frequency. This counter has been fabricated in TSMC 0.18μm CMOS process and the measurement results show that its clock frequency can be up to 1.6GHz and the power dissipation is 7.7mW under 1.8V power supply.
Keywords :
CMOS integrated circuits; counting circuits; low-power electronics; Straightforward circuit architecture; TSMC CMOS technology; clock frequency; frequency 1.6 GHz; full-custom methodology; logic effort; low-power up-down counter; manual placement; power 7.7 mW; size 0.18 mum; timing optimal methods; voltage 1.8 V; high-speed; true single phase clock(TSPC); up/down counter;
Conference_Titel :
Wireless Communications & Signal Processing (WCSP), 2012 International Conference on
Conference_Location :
Huangshan
Print_ISBN :
978-1-4673-5830-9
Electronic_ISBN :
978-1-4673-5829-3
DOI :
10.1109/WCSP.2012.6542792
