Title :
28nm high-k metal gate RRAM with fully compatible CMOS logic processes
Author :
Chin Yu Mei ; Wen Chao Shen ; Chih, Yu-Der ; Ya-Chin King ; Chrong Jung Lin
Author_Institution :
Microelectron. Lab., Nat. Tsing-Hua Univ., Hsinchu, Taiwan
Abstract :
A new 2-transistor logic ReRAM cell with 28nm high-k metal gate (HKMG) and fully CMOS logic compatible process is reported. The new 28nm logic compatible RRAM cell consists of two logic standard high-k metal gate CMOS transistors by an optimized composite resistive gate dielectric film TiN/HfO2/TiN as a storage node in the cell and as a gate dielectric in the select transistor. Using the cell gate as a source line for RRAM set/reset operation, the resistive memory states can be read and sensed by the selection of the select transistor and its bitline. As a result, the new 2-transistor CMOS logic ReRAM cell is very area-saving, cost effective, and fully compatible with advanced high-k metal gate CMOS logic technology platform. By adapting the highly manufacturable high-K gate dielectric in embedded ReRAM cell, the cell does not need any additional deposition of the resistive film or extra process steps, as a result, it will be easily scaled down and following by the CMOS technology evolution, besides it can be simply dropped on a logic IP or circuits for the need of NVM array or discrete storages in advanced SOC logic-NVM applications.
Keywords :
CMOS logic circuits; hafnium compounds; high-k dielectric thin films; random-access storage; titanium compounds; 2-transistor logic ReRAM cell; CMOS logic processes; CMOS technology; CMOS transistors; HKMG; RRAM set-reset operation; SOC logic-NVM applications; TiN-HfO2-TiN; composite resistive gate dielectric film; high-k gate dielectric; high-k metal gate RRAM; logic IP; logic circuits; resistive memory states; size 28 nm;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4673-3081-7
Electronic_ISBN :
978-1-4673-6422-5
DOI :
10.1109/VLSI-TSA.2013.6545590