Title :
Enabling thermal IL and ALD HfOx integration for sub-20nm gate stack
Author :
Hung, Stephen ; Mahapatra, Santanu ; Sato, Takao ; Bevan, M. ; Noori, Abdollah ; McDougal, B. ; Ni, C. ; Hong, Henry ; Lazik, C. ; Joshi, Kishor ; Mukhopadhyay, Saibal ; Rajamohanan, Bijesh ; Datta, Soupayan ; Liu, Peng ; Chu, Delin ; Date, L. ; Brand, A.
Author_Institution :
Appl. Mater. Inc., Sunnyvale, USA
Abstract :
World class EOT scaling and reliability performance has been achieved by integration (no air-break) of thermal interface layer (IL) and ALD high-k. RTP process is used for the formation of Ultra-Thin IL (UT-IL) and Mono-Layer IL (ML-IL). While integrated with ALD HfOx process, the resultant dielectric stack can reach 6Å EOT with excellent gate leakage, mobility and BTI reliability performances. The experiment also demonstrates that integrated thermal IL/HfOx stack provides lower pre-existing trap density and lower trap generation during BTI when compared to conventional chemical oxide IL/air-beak/HfOx stack.
Keywords :
atomic layer deposition; hafnium compounds; high-k dielectric thin films; leakage currents; monolayers; ALD high-k; ALD integration; BTI reliability; HfOx; dielectric stack; gate leakage; gate stack; monolayer interface layer; pre-existing trap density; thermal interface layer; trap generation; world class EOT scaling; 1f noise; Current measurement; Hafnium compounds; Logic gates; Oxidation; Reliability; Stress;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4673-3081-7
Electronic_ISBN :
978-1-4673-6422-5
DOI :
10.1109/VLSI-TSA.2013.6545613
