Title :
Improving and optimizing reliability in future technologies with high-κ dielectrics
Author :
Linder, B.P. ; Cartier, E. ; Krishnan, Sridhar ; Wu, E.
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Three mechanisms primarily limit gate oxide scaling: bias temperature instability in both NFETs (PBTI) and PFETs (NBTI), and gate dielectric breakdown in NFETs (nTDDB). Strategies for reducing each mechanism are identified, and the overall effect of each mechanism on future scaling is discussed. Specialized ring oscillator structures that aid in the understanding of the effect of both PBTI and NBTI on circuit operation are explored.
Keywords :
electric breakdown; field effect transistors; high-k dielectric thin films; integrated circuit reliability; negative bias temperature instability; NBTI; NFET; PBTI; PFET; bias temperature instability; gate dielectric breakdown; gate oxide scaling; high-k dielectrics; reliability; ring oscillator structures; Degradation; Dielectrics; Integrated circuit reliability; Logic gates; Stress; Transistors;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4673-3081-7
Electronic_ISBN :
978-1-4673-6422-5
DOI :
10.1109/VLSI-TSA.2013.6545622
