6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs

Author

Yi-Bo Liao ; Meng-Hsueh Chiang ; Damrongplasit, Nattapol ; Liu, T.-J King ; Wei-Chou Hsu

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2013

fDate

22-24 April 2013

Firstpage

1

Lastpage

2

Abstract

6T-SRAM cell design with gate-all-around (GAA) silicon nanowire (NW) MOSFETs is investigated via three-dimensional TCAD simulations and compact analytical modeling. A rectangular NW channel design allows the transistor width to be adjusted with reduced impact on short-channel effects. This in turn provides a means for tuning the cell ratios to optimize the tradeoff between static noise margin and writeability with optimal cell layout area efficiency.

Keywords

MOSFET; SRAM chips; electronic engineering computing; elemental semiconductors; nanowires; silicon; technology CAD (electronics); 6-T SRAM cell design; GAA silicon nanowire MOSFET; Si; gate-all-around silicon nanowire MOSFET; optimal cell layout area efficiency; rectangular NW channel design; short-channel effects; static noise margin; three-dimensional TCAD simulations; transistor; writeability; Logic gates; MOSFET; SRAM cells; Semiconductor device modeling; Silicon; Solid modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on

Conference_Location

Hsinchu

Print_ISBN

978-1-4673-3081-7

Electronic_ISBN

978-1-4673-6422-5

Type

conf

DOI

10.1109/VLSI-TSA.2013.6545631

Filename

6545631