Title :
CMOS image sensor design methodology
Author_Institution :
Semicond. Technol. Dev. Div., Sony Corp., Kanagawa, Japan
Abstract :
We developed the high quality CIS structure having the high saturation signal capacity with both the low dark current and the low noise using our FLAT structure integrating with a 2 × 4 pixel layout, having the high QE with the low crosstalk using our back illuminated structure.
Keywords :
1/f noise; CMOS image sensors; natural scenes; photodetectors; photography; 1/f noise; CMOS image sensor design; S/N ratio; backside illuminated CIS; dark current; mobile device; photograph scene; pixel pitch size; pixel structure; quantum efficiency; signal capacity; signal to noise ratio; 1f noise; Bismuth; Dark current; Diffraction; Silicon; Thermal noise;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4673-3081-7
Electronic_ISBN :
978-1-4673-6422-5
DOI :
10.1109/VLSI-TSA.2013.6545640
