Title :
Challenges and opportunities in small pixel development for novel CMOS image sensors
Author :
Shung Chieh ; Agranov, G. ; Hui Tian ; Baron, C. ; Hong-Wei Lee ; Madurawe, R.
Author_Institution :
Aptina Imaging Inc., San Jose, CA, USA
Abstract :
As pixels continue to shrink, increasingly complicated structures are being used to maintain performance. Some of these involve novel processes like wafer thinning and bonding, while others involve novel device or optical structures like light-pipes. The development of 3D interconnect and packaging technologies has also allowed new sensor structures to be developed that allow further customization to imaging. Whether these will be commercially viable, will depend on the cost-effectiveness of developing and manufacturing such structures. Despite the fact that increasingly complicated structures are being used, as we reach pixels with sizes 1.1um and below, system MTF does not continue to scale in performance with the increased pixel sampling frequency. However, the increased pixel sampling frequency can be used to support novel functionality such as High Dynamic Range Imaging or time-interleaved sampling for other applications like depth sensing and stereo vision.
Keywords :
CMOS image sensors; integrated circuit interconnections; integrated circuit packaging; sampling methods; 3D interconnect technology; CMOS image sensor; customization; packaging technology; pixel development; pixel sampling frequency; sensor structure; size 1.1 mum; High-speed optical techniques; Optical crosstalk; Optical imaging; Optical sensors; Photodiodes; Spatial resolution;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4673-3081-7
Electronic_ISBN :
978-1-4673-6422-5
DOI :
10.1109/VLSI-TSA.2013.6545642