DocumentCode :
610948
Title :
Accuracy-Performance Tradeoffs on an FPGA through Overclocking
Author :
Kan Shi ; Boland, David ; Constantinides, George A.
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
fYear :
2013
fDate :
28-30 April 2013
Firstpage :
29
Lastpage :
36
Abstract :
Embedded applications can often demand stringent latency requirements. While high degrees of parallelism within custom FPGA-based accelerators may help to some extent, it may also be necessary to limit the precision used in the datapath to boost the operating frequency of the implementation. However, by reducing the precision, the engineer introduces quantization error into the design. In this paper, we demonstrate that for many applications it would be preferable to simply overclock the design and accept that timing violations may arise. Since the errors introduced by timing violations occur rarely, they will cause less noise than quantization errors. Through the use of analytical models and empirical results on a Xilinx Virtex-6 FPGA, we show that a geometric mean reduction of 67.9% to 98.8% in error expectation or a geometric mean improvement of 3.1% to 27.6% in operating frequency can be obtained using this alternative design methodology.
Keywords :
embedded systems; field programmable gate arrays; logic design; FPGA-based accelerators; Xilinx Virtex-6; accuracy-performance tradeoffs; analytical models; embedded applications; error expectation; geometric mean reduction; overclocking; quantization error; stringent latency requirements; timing violations; Adders; Clocks; Delays; Field programmable gate arrays; Finite wordlength effects; Probabilistic logic; FPGA; overclocking; probabilistic design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Custom Computing Machines (FCCM), 2013 IEEE 21st Annual International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4673-6005-0
Type :
conf
DOI :
10.1109/FCCM.2013.10
Filename :
6545991
Link To Document :
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