A Delay-based PUF Design Using Multiplexers on FPGA

Author

Miaoqing Huang ; Shiming Li

Author_Institution

Dept. of Comput. Sci. & Comput. Eng., Univ. of Arkansas, Fayetteville, AR, USA

fYear

2013

fDate

28-30 April 2013

Firstpage

226

Lastpage

226

Abstract

Summary form only given. Physically unclonable functions (PUFs) have been a hot research topic in hardware-oriented security for many years. Given a challenge as an input to the PUF, it generates a corresponding response, which can be treated as a unique fingerprint or signature for authentication purpose. In this paper, a delay-based PUF design involving multiplexers on FPGA is presented. Due to the intrinsic difference of the switching latencies of two chained multiplexers, a positive pulse may be produced at the output of the downstream multiplexer. This pulse can be used to set the output of a D flip-flop to `1´. The proposed design improves the randomness of the outputs of the PUF.

Keywords

field programmable gate arrays; logic design; security of data; FPGA; authentication purpose; delay-based PUF design; downstream multiplexer; field programmable gate array; flip-flop; hardware-oriented security; multiplexer; multiplexers; physically unclonable function; switching latency; Computer science; Computers; Educational institutions; Electronic mail; Field programmable gate arrays; Multiplexing; Table lookup; FPGA; delay-based PUF; physically unclonable function;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Custom Computing Machines (FCCM), 2013 IEEE 21st Annual International Symposium on

Conference_Location

Seattle, WA

Print_ISBN

978-1-4673-6005-0

Type

conf

DOI

10.1109/FCCM.2013.11

Filename

6546023