• DocumentCode
    610982
  • Title

    FPGA Simulation Engine for Customized Construction of Neural Microcircuit

  • Author

    Cong, J. ; Blair, Hugh T. ; Di Wu

  • Author_Institution
    Dept. of Comput. Sci., Univ. of California, Los Angeles, Los Angeles, CA, USA
  • fYear
    2013
  • fDate
    28-30 April 2013
  • Firstpage
    229
  • Lastpage
    229
  • Abstract
    In this poster we describe a platform-based approach for rapid construction of FPGA-based simulation of neural microcircuits composed from integrate-and-fire (IAF) neurons. Our approach exploits high-level synthesis to bypass the high design complexity of RTL coding, and enables automatic optimization and design space exploration. We demonstrate the benefits of this approach by simulating a neural microcircuit that performs oscillatory path integration, which evidence suggests may be a critical building block of the navigation system inside a rodent´s brain. Experiments show that our FPGA simulation engine can achieve up to 23x speedup and 450x energy reduction compared to commodity CPU. The methodology described in this paper should be broadly applicable for creating FPGA simulations over a wide range neural microcircuit architectures.
  • Keywords
    field programmable gate arrays; high level synthesis; neural chips; FPGA simulation engine; IAF neuron; RTL coding; design space exploration; field programmable gate array; high-level synthesis; integrate-and-fire neuron; neural microcircuit; oscillatory path integration; platform-based approach; register transfer level; Computational modeling; Educational institutions; Engines; Field programmable gate arrays; Neural microtechnology; Neurons; Pipelines;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field-Programmable Custom Computing Machines (FCCM), 2013 IEEE 21st Annual International Symposium on
  • Conference_Location
    Seattle, WA
  • Print_ISBN
    978-1-4673-6005-0
  • Type

    conf

  • DOI
    10.1109/FCCM.2013.22
  • Filename
    6546026