• DocumentCode
    6119
  • Title

    CORDIC Designs for Fixed Angle of Rotation

  • Author

    Meher, Pramod Kumar ; Park, Sung Yun

  • Author_Institution
    Inst. for Infocomm Res., Agency for Sci., Technol. & Res. (A*STAR), Singapore, Singapore
  • Volume
    21
  • Issue
    2
  • fYear
    2013
  • fDate
    Feb. 2013
  • Firstpage
    217
  • Lastpage
    228
  • Abstract
    Rotation of vectors through fixed and known angles has wide applications in robotics, digital signal processing, graphics, games, and animation. But, we do not find any optimized coordinate rotation digital computer (CORDIC) design for vector-rotation through specific angles. Therefore, in this paper, we present optimization schemes and CORDIC circuits for fixed and known rotations with different levels of accuracy. For reducing the area- and time-complexities, we have proposed a hardwired pre-shifting scheme in barrel-shifters of the proposed circuits. Two dedicated CORDIC cells are proposed for the fixed-angle rotations. In one of those cells, micro-rotations and scaling are interleaved, and in the other they are implemented in two separate stages. Pipelined schemes are suggested further for cascading dedicated single-rotation units and bi-rotation CORDIC units for high-throughput and reduced latency implementations. We have obtained the optimized set of micro-rotations for fixed and known angles. The optimized scale-factors are also derived and dedicated shift-add circuits are designed to implement the scaling. The fixed-point mean-squared-error of the proposed CORDIC circuit is analyzed statistically, and strategies for reducing the error are given. We have synthesized the proposed CORDIC cells by Synopsys Design Compiler using TSMC 90-nm library, and shown that the proposed designs offer higher throughput, less latency and less area-delay product than the reference CORDIC design for fixed and known angles of rotation. We find similar results of synthesis for different Xilinx field-programmable gate-array platforms.
  • Keywords
    digital arithmetic; field programmable gate arrays; mean square error methods; optimisation; signal processing; Synopsys Design Compiler; TSMC library; Xilinx field-programmable gate-array; area-complexity; barrel-shifters; bi-rotation CORDIC units; cascading dedicated single-rotation units; coordinate rotation digital computer; dedicated shift-add circuits; fixed-angle rotations; fixed-point mean-squared-error; hardwired pre-shifting scheme; high-throughput; known rotations; microrotations; optimization schemes; reduced latency implementations; scaling; size 90 nm; time-complexity; vector-rotation; Accuracy; Adders; Complexity theory; Digital signal processing; Optimization; Registers; Vectors; Coordinate rotation digital computer (CORDIC); VLSI; digital arithmetic; digital signal processing (DSP) chip;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2012.2187080
  • Filename
    6165685