Digital PWM of cascaded multilevel voltage source inverter using FPGA

Multilevel inverter finds its application in high voltage and high power converters. Various topologies of multilevel inverter provides several advantages including lower voltage stress, higher efficiency, lower EMI, better waveform and improved THD. This paper presents the development of Altium FPGA as a control circuit for generation of the digital pulse width modulation (DPWM) signal for the single-phase cascaded H-bridge multilevel inverter. The FPGA chip is chosen for the hardware implementation due to its ability to produce accurate results at a high computational speed. Counter based digital pulse width modulation (DPWM) for increased resolution without unnecessarily increasing the clock frequency is used. In addition to Altium Nanoboard FPGA, Xilinx System Generator/MATLAB software has been used for simulation and verification of the proposed circuit before implementation. The simulation and experimental results are in close agreement.