DocumentCode :
612259
Title :
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface
Author :
Miura, Naruhisa ; Koizumi, Yuki ; Sasaki, Erika ; Take, Y. ; Matsutani, Hiroshi ; Kuroda, Tadahiro ; Amano, Hideharu ; Sakamoto, R. ; Namiki, Mitaro ; Usami, Kimiyoshi ; Kondo, Makoto ; Nakamura, Hajime
Author_Institution :
Keio Univ., Yokohama, Japan
fYear :
2013
fDate :
17-19 April 2013
Firstpage :
1
Lastpage :
3
Abstract :
A scalable heterogeneous multi-core processor is developed. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multi-core accelerators improves computational energy efficiency by proper task assignment and massive parallel computing. The stacked chips interconnect through a scalable 3D Network on Chip (NoC). By simply changing the number of stacked accelerator chips, processor parallelism can be widely scaled. In combination with Dynamic Voltage and Frequency Scaling (DVFS), the energy efficiency can be optimized for various performance requirements. No design change is needed, and hence no additional Non-Recurring Engineering (NRE) cost. An inductive-coupling ThruChip Interface (TCI) is applied to stacked-chip communications, forming a low-cost and robust high-speed 3D NoC. A prototype demonstration system has been developed with 65nm CMOS test chips. Successful system operations including 10-hours continuous Linux OS operation are confirmed for the first time.
Keywords :
CMOS digital integrated circuits; Linux; electronic engineering computing; integrated circuit interconnections; multiprocessing systems; network-on-chip; CMOS test chips; DVFS; NRE cost; computational energy efficiency; continuous Linux OS operation; dynamic voltage and frequency scaling; energy efficiency; general-purpose CPU; inductive-coupling TCI; inductive-coupling thruchip interface; low-cost high-speed 3D NoC; nonrecurring engineering cost; parallel computing; processor parallelism; reconfigurable multicore accelerators; robust high-speed 3D NoC; scalable 3D NoC; scalable 3D heterogeneous multicore processor; scalable 3D network on chip; size 65 nm; stacked accelerator chips; stacked-chip communications; task assignment; Arrays; CMOS integrated circuits; Clocks; Energy efficiency; Multicore processing; Stacking; Three-dimensional displays;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Cool Chips XVI (COOL Chips), 2013 IEEE
Conference_Location :
Yokohama
Print_ISBN :
978-1-4673-5780-7
Electronic_ISBN :
978-1-4673-5781-4
Type :
conf
DOI :
10.1109/CoolChips.2013.6547916
Filename :
6547916
Link To Document :
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