Title :
Power efficient realtime super resolution by virtual pipeline technique on a server with manycore coprocessors
Author :
Ishizaka, K. ; Miyamoto, Takahiro ; Akimoto, S. ; Iketani, A. ; Hosomi, T. ; Sakai, J.
Author_Institution :
NEC Corp., Kawasaki, Japan
Abstract :
Super Resolution image processing (SR) is a heavy task for a today´s mid-range Xeon server. To accelerate SR, we utilize a server system with manycore coprocessor, Intel Xeon Phi coprocessor. Function offload model is a usual execution model for those systems. However it is difficult for SR to increase utilization of both host processors and coprocessors by the model. We propose a virtual pipeline model which can fully utilize both processors. Experimental results show that our SR improves performance 3.3 times and performance/watt 1.5 times. Our SR achieves 30 frames per sec from SD to HD.
Keywords :
coprocessors; image resolution; pipeline processing; Intel Xeon Phi coprocessor; Xeon server; execution model; function offload model; manycore coprocessors; power efficient realtime super resolution; super resolution image processing; virtual pipeline model; virtual pipeline technique; Coprocessors; Image reconstruction; Image resolution; Optical imaging; Pipelines; Program processors; Servers; Coprocessor; Manycore; Power Efficiency; Super Resolution;
Conference_Titel :
Cool Chips XVI (COOL Chips), 2013 IEEE
Conference_Location :
Yokohama
Print_ISBN :
978-1-4673-5780-7
Electronic_ISBN :
978-1-4673-5781-4
DOI :
10.1109/CoolChips.2013.6547918
