Title :
SOC test compression scheme using sequential linear decompressors with retained free variables
Author :
Muthyala, Sreenivaas S. ; Touba, Nur A.
Author_Institution :
Comput. Eng. Res. Center, Univ. of Texas, Austin, TX, USA
fDate :
April 29 2013-May 2 2013
Abstract :
A highly efficient SOC test compression scheme which uses sequential linear decompressors local to each core is proposed. Test data is stored on the tester in compressed form and brought over the TAM to the core before being decompressed. Very high encoding efficiency is achieved by providing the ability to share free variables across test cubes being compressed at the same time as well as in subsequent time steps. The idea of retaining unused non-pivot free variables when decompressing one test cube to help for encoding subsequent test cubes that was introduced in [Muthyala 12] is applied here in the context of SOC testing. It is shown that in this application, a first-in first-out (FIFO) buffer is not required. The ability to retain excess free variables rather than wasting them when the decompressor is reset avoids the need for high precision in matching the number of free variables used for encoding with the number of care bits. This allows greater flexibility in test scheduling to reduce test time, tester storage, and control complexity as indicated by the experimental results.
Keywords :
buffer circuits; circuit complexity; integrated circuit testing; system-on-chip; FIFO buffer; SOC test compression scheme; TAM; control complexity; first-in first-out buffer; nonpivot free variables; retained free variables; sequential linear decompressors; system-on-chip design; test access mechanisms; test cubes; test data; test scheduling; test time reduction; tester storage; very high encoding efficiency; Clocks; Computer architecture; Encoding; Equations; Schedules; System-on-chip; Testing;
Conference_Titel :
VLSI Test Symposium (VTS), 2013 IEEE 31st
Conference_Location :
Berkeley, CA
Print_ISBN :
978-1-4673-5542-1
DOI :
10.1109/VTS.2013.6548884