DocumentCode :
613038
Title :
Innovative practices session 11C: Resilience
Author :
Cher, Chen-Yong ; Kumar, Mohan J.
Author_Institution :
IBM
fYear :
2013
fDate :
April 29 2013-May 2 2013
Firstpage :
1
Lastpage :
1
Abstract :
Software Hardware co-design is a key mechanism to realizing reliability at platform level. While error avoidance is the ideal, it is not always practical in an economic sense. Often used technique is to detect errors in hardware and implement the recovery in coordination with software. This talk will discuss some examples of such coordination on Intel Xeon (e.g., DIMM Sparing, MCA recovery) and the implications of this type of solution such as platform validation, interface standardization, software enablement, etc.
Keywords :
Abstracts; Hardware; Integrated circuit reliability; Reliability engineering; Software; Software reliability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium (VTS), 2013 IEEE 31st
Conference_Location :
Berkeley, CA
ISSN :
1093-0167
Print_ISBN :
978-1-4673-5542-1
Type :
conf
DOI :
10.1109/VTS.2013.6548943
Filename :
6548943
Link To Document :
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