FPGA architecture for fast floating point matrix inversion using uni-dimensional systolic array based structure

This paper describes the structure of fast matrix inversion on FPGA. The structure is derived from the systolic array algorithm and revised to the uni-dimensional array to lower the resources consumption for practical use. Input matrix, with single precision floating point elements, is inverted in 5n²+4n-3 time ticks. Both mantissa and exponent processing units are proposed to be easily implemented on FPGA. Comparison of the structure with inversion using MicroBlaze soft CPU is presented.