Effect of plasticity of copper in Through Silicon Vias on mobility of carriers in active device areas

Scaling down the dimensions of active devices is becoming increasingly difficult as silicon is approaching its physical material limits. 3D integration of logic and memory devices has emerged as a solution to the bandwidth and power efficiency challenges. Mechanical stress induced by Through Silicon Vias (TSVs) is one of the main constraints that have to be controlled to preserve the integrity of front end devices. The plastic behavior of copper used in TSVs is simulated in this work. The simulations make use of experimental data that were recently published [1]. Elastic and plastic parameters of copper are extracted from the simulations. Those parameters are used for simulating a necessary anneal step after TSV deposition. Stress resulting from the mismatch in coefficients of thermal expansion between copper and silicon affects the mobility of carriers in active device areas. The effect of stress on mobility is quantified.