Timing yield and reliability improvement of carbon nano-tube FET based digital circuits with statistical driven correlation-aware placement

Carbon Nano-tube Field Effect Transistor (CNFET) is one of the most promising successors of CMOS technology because of its superb electrical features. Although these features are proper for implementing in various practical circuits, CNFET-based circuits will encounter enormous fabrication problems due to their size. Two of the most challenging problems are timing yield and reliability reduction. Consequently methods for improving robustness of CNFET-based circuits should be conducted. Considering these problems, in this paper, the statistical model of reliability and timing yield of CNFET-based circuits is presented and then we propose a statistical driven correlation-aware placement for CNFET-based gates. We illustrate that our placement engine improves the reliability and timing yield of various circuits. Following these observations, in our method, a statistical approach is conducted to get optimum timing yield of register-to-register path in a sequential circuit. Subsequently, experimental results show improvement of about 19% in timing yield and 17% in reliability of some ISCAS89 circuits.