DocumentCode :
614933
Title :
Designing product workflow for logistics a hidden potential for cycle time and cost reduction as well as quality improvement in high-tech-factories
Author :
Keil, Stefan ; Eberts, Dietrich ; Lasc, Rainer
Author_Institution :
Fac. of Bus. & Econ., Dresden Univ. of Technol., Dresden, Germany
fYear :
2013
fDate :
14-16 May 2013
Firstpage :
27
Lastpage :
34
Abstract :
Customers demand more and more integrated functions on one chip. Therefore product complexity is increasing tremendously. This results in increasing production process complexity, reflected in additional lithography layers for example which causes longer cycle times, higher costs and extended feedback loops for quality improvement. Each additional process step requires at least five additional logistics steps as each lot has to be handled and transported twice and stored temporarily. This scenario is leading in a `logistical trap´ with a high proportion of non-value adding time. Main leverage to improve long lead times is design of product workflow for logistics which is the focus of the contribution.
Keywords :
cost reduction; customer satisfaction; lithography; logistics; quality management; semiconductor device manufacture; cost reduction; customer demand; high-tech-factories; lithography; logistics; product complexity; product workflow design; production process complexity; quality improvement; Cleaning; Complexity theory; Logistics; Materials; Time measurement; DjM; design for logistics; improve quality by shorter feedback loops; redesinging product workflow; reducing cycle time and costs;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Semiconductor Manufacturing Conference (ASMC), 2013 24th Annual SEMI
Conference_Location :
Saratoga Springs, NY
ISSN :
1078-8743
Print_ISBN :
978-1-4673-5006-8
Type :
conf
DOI :
10.1109/ASMC.2013.6552770
Filename :
6552770
Link To Document :
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