Title :
Use of performance path test to optimize yield
Author :
Bickford, Jeanne Paulette ; Jinjun Xiong
Author_Institution :
IBM Syst. & Technol. Group, ASIC & IP Dev., Essex Junction, VT, USA
Abstract :
Performance path test provides an innovative alternative to PSRO performance screens and functional pattern test for manufacturing performance screening. The process window sigma associated with a desired screen point is used in a special timing run to create the expected delay for paths in the product. These expected delays are used to screen products. Products passing this test will meet requirements in client applications. Parts that fail will not meet product design assumptions and are not shipped. Performance path test avoids yield loss, false accept, and false reject problems associated with use of edge PSRO monitors.
Keywords :
integrated circuit yield; optimisation; oscillators; semiconductor device manufacture; semiconductor device testing; PSRO monitors; PSRO performance screens; functional pattern test; manufacturing performance screening; performance path test; performance screen ring oscillators; process window sigma; screen point; screen products; yield optimization; Automatic test pattern generation; Delays; Integrated circuit modeling; Loss measurement; Manufacturing; Performance evaluation; Fmax; performance; timing; yield optimization;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference (ASMC), 2013 24th Annual SEMI
Conference_Location :
Saratoga Springs, NY
Print_ISBN :
978-1-4673-5006-8
DOI :
10.1109/ASMC.2013.6552806
