DocumentCode
614968
Title
Statistical correlation of inline defect to sort test in semiconductor manufacturing
Author
Hessinger, Uwe ; Chan, W. ; Schafman, Brett ; Toan Nguyen ; Burt, Shiree
Author_Institution
Foundry Oper., Lattice Semicond. Corp., Hillsboro, OR, USA
fYear
2013
fDate
14-16 May 2013
Firstpage
212
Lastpage
219
Abstract
A yield analysis method using basic yield and inline defect information to statistically determine significant root-causes of yield loss in semiconductor manufacturing is presented. Using simple statistics on pass/fail die and defect maps, the goal of this method is to provide the fab process line with feedback on the yield loss impact for defect inspected process layers. Quantifying these losses, in terms of yield loss percent and statistical confidence allows the fab to set priorities for defect reduction work and achieve maximum yield enhancement. Using statistics, valid yield loss sources can be separated from nonkiller or nuisance defects. This tool can also be used to select the most effective inspection tool or recipe for a given inspection layer. Results are readily integrated with additional yield analysis results for a comprehensive yield loss accounting system.
Keywords
inspection; semiconductor industry; statistical analysis; defect inspected process layers; defect maps; defect reduction work; fab process; inline defect statistical correlation; inspection layer; inspection tool; nonkiller defects; nuisance defects; semiconductor manufacturing; sort test; statistical confidence; Correlation; Failure analysis; Inspection; Manufacturing; Probability; Sensitivity; Yield estimation; Kill Ratio; Probability; Statistics; Yield; Yield Learning;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference (ASMC), 2013 24th Annual SEMI
Conference_Location
Saratoga Springs, NY
ISSN
1078-8743
Print_ISBN
978-1-4673-5006-8
Type
conf
DOI
10.1109/ASMC.2013.6552807
Filename
6552807
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