Case studies of fault isolation for the global failing patterns on SRAM bitmap caused by the defects in peripheral logic regions

Product-like functional SRAM test chips have been widely used to capture systematic yield loss mechanisms during yield learning. Especially in early technology development, the top failing modes contributing to bit loss count are global patterns in the SRAM bitmap, which are highly suspected to be caused by defects in the peripheral control circuits. This paper describes a fault isolation flow on for global patterns which combines bitmap analysis, SRAM functional test debugging, circuit layout tracing analysis and physical failure analysis.