• DocumentCode
    61563
  • Title

    Fast Inversion in {schmi{GF(2^m)}} with Normal Basis Using Hybrid-Double Multipliers

  • Author

    Azarderakhsh, Reza ; Jarvinen, Kimmo ; Dimitrov, Vassil

  • Author_Institution
    Dept. of Comput. Eng., Rochester Inst. of Technol., Rochester, NY, USA
  • Volume
    63
  • Issue
    4
  • fYear
    2014
  • fDate
    Apr-14
  • Firstpage
    1041
  • Lastpage
    1047
  • Abstract
    Fast inversion in finite fields is crucial for high-performance cryptography and codes. We present techniques to exploit the recently proposed hybrid-double multipliers for fast inversions in binary fields GF(2m) with normal bases. A hybrid-double multiplier computes a double multiplication, the product of three elements in GF(2m), with a latency comparable to the latency of single multiplication of two elements. Traditional approaches, such as Itoh-Tsujii, cannot utilize hybrid-double multipliers. We devise a new inversion algorithm based on ternary representations that exploits their potential. The algorithm reduces the latency of inversion significantly for the fields recommended by NIST if hybrid-double multipliers are employed. For example, the algorithm computes an inversion in GF(2163) with only five double multiplications whereas the Itoh-Tsujii algorithm requires nine single or double multiplications. We propose a new inverter architecture using this new algorithm and a hybrid-double multiplier. We show that it is faster than the existing techniques by providing ASIC synthesis results using 65-nm CMOS technology. For example, our inverter for GF(2163) achieves about 34 percent shorter computation time than an inverter using the Itoh-Tsujii algorithm and a single multiplier.
  • Keywords
    codes; cryptography; ASIC synthesis; CMOS technology; Itoh-Tsujii; Itoh-Tsujii algorithm; cryptography; double multiplication; fast inversion; hybrid double multiplier; hybrid double multipliers; inverter architecture; normal basis; single multiplication; Computer architecture; Delay; Gaussian processes; Inverters; Logic gates; NIST; Registers; ASIC; Finite field; Itoh-Tsujii; binary extension field; codes; cryptography; hybrid-double multiplier; inversion; normal basis;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2012.265
  • Filename
    6338926