Real-time processing of multi-frequency eddy currents testing signals

In this paper, a real-time Digital Signal Processing (DSP) architecture is proposed to generate and process multi-frequency signals for eddy currents testing. This architecture was implemented on a dedicated instrument whose processing core is a Field-Programmable Gate Array (FPGA) for DSP purposes. Stimulus generation is achieved using Direct Digital Synthesis (DDS) with some improvements to remove spurious frequency components. An In-phase and Quadrature (IQ) demodulation scheme is implemented to estimate the real and imaginary part of the probes output signals. A Cascaded Integrator Comb (CIC) decimator is used to lower the sampling frequency allowing narrowband IIR filtering using low resources. The proposed architecture is able to generate and process the stimulus and input data at 125 MSamples/s and to estimate the input data components at 1.25 MSamples/s rate for frequencies between 50 kHz and 10 MHz.