Title :
Data compression using mixed cascade of nonlinear logic
Author :
Das, Sunil R. ; Shaw, Danny L. ; Biswas, Satyendra N. ; Assaf, Mansour H. ; Morton, S. ; Ozkarahan, Irem ; Petriu, Emil M. ; Groza, V.
Author_Institution :
Dept. of Comput. Sci., Troy Univ., Montgomery, AL, USA
Abstract :
The subject paper presents new approach to response data compaction of multi-output digital circuits using two-input nonlinear logic with the objective of designing zeroaliasing (aliasing-free) space compression hardware for single stuck-line faults, extending well-known concept of conventional switching theory, viz. that of compatibility relation as used in the minimization of incompletely specified sequential machines. For a pair of response data outputs of the circuit under test (CUT), the method introduces the notion of fault detection compatibility and conditional fault detection compatibility (conditional upon some other pair of response data outputs being simultaneously fault detection compatible) with respect to two-input AND/NAND and/or OR/NOR logic. The process is illustrated with the design details of space compressors for the International Symposium on Circuits and Systems or ISCAS 85 combinational and ISCAS 89 full-scan sequential benchmark circuits using simulation programs ATALANTA, FSIM and COMPACTEST, though, because of space constraints, only some partial results on simulation on ISCAS 89 full-scan sequential benchmark circuits using ATALANTA are provided here.
Keywords :
NAND circuits; NOR circuits; benchmark testing; circuit simulation; circuit testing; combinational circuits; data compression; fault diagnosis; logic design; logic testing; nonlinear network synthesis; sequential circuits; switching theory; ATALANTA simulation program; COMPACTEST simulation program; CUT; FSIM simulation program; ISCAS 85 combinational circuit; ISCAS 89 full-scan sequential benchmark circuit; International Symposium on Circuits and Systems; circuit under test; conditional fault detection; data compression; fault detection compatibility; mixed cascade; multioutput digital circuit; response data compaction output; sequential machine minimization; single stuck-line fault; switching theory; two-input AND-NAND logic circuit; two-input OR-NOR logic circuit; two-input nonlinear logic circuit; zero-aliasing space compression hardware; Benchmark testing; Built-in self-test; Circuit faults; Compaction; Integrated circuit modeling; Logic gates; ATALANTA; Aliasing-free (zero-aliasing) space compaction; built-in self-testing in very large scale integration circuits and systems; fault detection and conditional fault detection compatibility;
Conference_Titel :
Instrumentation and Measurement Technology Conference (I2MTC), 2013 IEEE International
Conference_Location :
Minneapolis, MN
Print_ISBN :
978-1-4673-4621-4
DOI :
10.1109/I2MTC.2013.6555673
