• DocumentCode
    61753
  • Title

    PC-TRIO: A Power Efficient TCAM Architecture for Packet Classifiers

  • Author

    Banerjee, Tania ; Sahni, Sartaj ; Seetharaman, Gunasekaran

  • Author_Institution
    Dept. of Comput. & Inf. Sci. & Eng., Univ. of Florida, Gainesville, FL, USA
  • Volume
    64
  • Issue
    4
  • fYear
    2015
  • fDate
    April 1 2015
  • Firstpage
    1104
  • Lastpage
    1118
  • Abstract
    PC-TRIO is an indexed TCAM architecture for packet classification. In addition to index TCAMs, PC-TRIO uses wide SRAM words. On our packet classifier data sets, PC-TRIO reduced TCAM power by 96 percent and lookup time by 98 percent on an average, compared to PC-DUOS+ [28] that does not use indexing or wide SRAMs. PC-DUOS+ was shown to be better than STCAM, which is a single TCAM architecture conventionally used for packet classification [28]. In this paper, we also extend PC-DUOS+ by augmenting it with wide SRAMs and index TCAMs using the same methodology as used in PC-TRIO, to obtain PC-DUOS+W. On ACL data sets, PC-DUOS+W reduced TCAM power by 86 percent and lookup time by 98 percent, compared to PC-DUOS+, which demonstrates the effectiveness of indexing and usage of wide SRAMs in reducing power and lookup time for packet classifiers.
  • Keywords
    SRAM chips; content-addressable storage; memory architecture; ACL data sets; PC-DUOS+; PC-DUOS+W; PC-TRIO; SRAM words; lookup time; packet classifier data sets; power efficient TCAM architecture; Computer architecture; Hardware; Indexes; Ports (Computers); Power demand; Random access memory; Throughput; Packet classifier; TCAM; incremental updates; power;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2014.2315645
  • Filename
    6782645