ASIC based logarithmic multiplier using iterative pipelined architecture

Multiplication is a significant process in digital signal processing algorithms. These algorithms involve large number of multiplications, which is time consuming. In digital signal applications time is more important as compared to accuracy. In this paper a simple and efficient architecture of multiplier is proposed which uses adders, shifters, encoders and decoder etc. that consume less area, time and power. The multiplication is based on Mitchell´s algorithm. This multiplier gives arbitrary accuracy but with only two iterations it gives very less error that is limited to 2% which is tolerable in digital signal algorithms. This multiplier is implemented in ASIC using SOC encounter and NCSIM simulator in Cadence with 180nm technology for 16 bit operands at 12.5 MHz frequency.