DocumentCode
618330
Title
FPGA implementation of low bandwidth ECC code
Author
Sivan, Silpa ; Katta, S. ; Venkatesulu, P. ; Nayaka, Raja Jitendra
fYear
2013
fDate
11-12 April 2013
Firstpage
468
Lastpage
472
Abstract
In this paper a method to detect two simultaneous bit errors and correct a single bit error during data transmission is devised. The proposed method is developed based on Hamming Code. The key point for the implementation of error-free data transmission is the encoding of the information to be transmitted in such a way that some extent of redundancy is included in the encoded data, and a method for efficient decoding at the receiver is available. These two requirements have been achieved in the new method in an efficient and simple way. In this paper, one bandwidth reduction technique is included along with Hamming code. The proposed method is implemented using XILINX, and has been demonstrated through examples.
Keywords
Hamming codes; data communication; decoding; error correction codes; field programmable gate arrays; redundancy; FPGA implementation; Hamming code; XILINX; bandwidth reduction technique; decoding; error-free data transmission; information encoding; low bandwidth ECC code; redundancy; simultaneous bit error detection; single bit error correction; Bandwidth; Clocks; Data communication; Multiplexing; Radiation detectors; Receivers; Redundancy; Double Data Rate Transmission; FPGA; Hamming code; Parity Method; Redundancy Bits;
fLanguage
English
Publisher
ieee
Conference_Titel
Information & Communication Technologies (ICT), 2013 IEEE Conference on
Conference_Location
JeJu Island
Print_ISBN
978-1-4673-5759-3
Type
conf
DOI
10.1109/CICT.2013.6558141
Filename
6558141
Link To Document