Parity preserving logic based fault tolerant reversible ALU

Author

Rakshith, T.R. ; Saligram, Rakshith

Author_Institution

Telecommun., R.V. Coll. of Eng., Bangalore, India

fYear

2013

fDate

11-12 April 2013

Firstpage

485

Lastpage

490

Abstract

Power dissipation is an important design criterion during the VLSI process flow. Reversible logic is one of the promising fields having a wide range of applications starting from low power VLSI design, fault tolerant circuits, quantum computing to fields such as bio informatics. An ALU may be regarded as the processor´s numerical calculator and logical operation evaluator. In this paper a fault tolerant reversible ALU design is proposed. Parity preserving logic gates are the main component in this design. A parity preserving gate is the one in which the parity of the input and the output vectors is the same. The proposed ALU can produce up to 16 logical and 16 arithmetic operations.

Keywords

VLSI; bioinformatics; digital arithmetic; fault tolerance; logic design; logic gates; low-power electronics; quantum computing; VLSI process flow; arithmetic logic unit; arithmetic operations; bioinformatics; design criterion; fault tolerant circuits; fault tolerant reversible ALU design; logical operation evaluator; low power VLSI design; parity preserving logic gates; power dissipation; quantum computing; reversible logic; Communications technology; Conferences; Fault tolerance; Fault tolerant systems; Logic gates; Signal generators; Vectors; ALU; Revesible Logic; fault tolerance; parity preserving gates; quantum computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Information & Communication Technologies (ICT), 2013 IEEE Conference on

Conference_Location

JeJu Island

Print_ISBN

978-1-4673-5759-3

Type

conf

DOI

10.1109/CICT.2013.6558144

Filename

6558144